Call for papers

Synopsis

FPT conference is the premier conference in the Asia-Pacific region on field-programmable technologies including reconfigurable computing devices and systems containing such components.

Field-programmable devices promise the flexibility of software with the performance of hardware. The development and application of field-programmable technology have become important topics of research and development. Field-programmable technology is widely applied, in high-performance computing systems, embedded and low-power control instruments, mobile communications, rapid prototyping and product emulation, among other areas.

Important Dates

We will be accepting papers in three streams: Journal Track, Conference Track and PhD Forum. Papers submitted to the journal track will not be eligible to be re-submitted to the conference track

Journal Track

Submission Instructions for Journal Track

DateEvent
30 June 2024Submission Deadline
8 August 2024Initial reviews available
8 September 2024Revision 1 Deadline
11 October 2024Notification regarding decision to accept to present at FPT 2024 or move to standard TRETS track
Conference Track

Submission Instructions for Conference Track

DateEvent
14 July 2024Title and abstract due
21 July 2024Paper submission due
13 September 2024Initial reviews/rebuttal questions available
20 September 2024Rebuttal responses due
11 October 2024Notification
PhD Forum

Submission Instructions for Ph.D. Forum

DateEvent
15 September 2024Title and abstract due
22 September 2024Submission Deadline
11 October 2024Notification
13 September 2024Initial reviews/rebuttal questions available

Scope and Expectations

Submissions are solicited on new research results and detailed tutorial expositions related to field-programmable technologies, including but not limited to:

  • Tools and Design Techniques for field-programmable technology including placement, routing, synthesis, verification, debugging, runtime support, technology
    mapping, partitioning, parallelization, timing optimization, design and run-time environments, high-level synthesis (HLS) compilers, languages and modeling techniques,
    provably-correct development, intellectual property core-based design, domain-specific development, hardware/software co-design.
  • Architectures for field-programmable technology including field-programmable gate arrays, complex programmable logic devices, coarse-grained reconfigurable arrays,
    field- programmable interconnect, field-programmable analogue arrays, field-programmable arithmetic arrays, memory architectures, interface technologies, low-power
    techniques, adaptive devices, reconfigurable computing systems, high-performance reconfigurable systems, evolvable hardware and adaptive computing, fault tolerance and
    avoidance.
  • Device technology for field-programmable logic including programmable memories such as non- volatile, dynamic and static memory cells and arrays, interconnect
    devices, circuits and switches, and emerging VLSI device technologies.
  • Applications of field-programmable technology including accelerators for biomedical / scientific / neuro-morphic computing and machine learning, network processors,
    real-time systems, rapid prototyping, hardware emulation, digital signal processing, interactive multimedia, machine vision, computer graphics, cryptography, robotics,
    manufacturing systems, embedded applications, evolvable and biologically-inspired hardware.
  • Education for field-programmable technology including courses, teaching and training experience, experiment equipment, design and applications.
    Note that simply implementing an application using an FPGA is not considered a sufficient research contribution. Application-based papers should emphasize novel design
    techniques, novel use of embedded resources, or clearly articulated and measured system performance benefits.

Note that simply implementing an application using an FPGA is not considered a sufficient research contribution. Application-based papers should emphasize novel design techniques, novel use of embedded resources, or clearly articulated and measured system performance benefits.

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