Time	Day 1 (Dec. 10)	Time	Day 2 (Dec. 11)	Time	Day 3 (Dec. 12)
9:00~9:40	Registration
9:40~10:00	Opening
10:00~11:00	Session 1 (Applications I)	9:30~10:50	Session 4 (Programmable Fabrics)	9:30~10:20	Session 6 (High Level Synthesis)
	Morning Tea		Morning Tea & Poster Session		Morning Tea & Poster Session
11:30~12:30	Journal Session 1	12:00~13:00	Panel	11:00- 12:00	Journal Session II
				12:00- 13:00	Keynote II, Richard Y. Sun, S2C Limited
	Lunch	Lunch		13:00~13:20	Closing
13:30~14:30	Keynote I, Wang Yu, Tsinghua University, Towards Energy Efficient Circuit and System Design for AI 2.0 Era	13:30~14:30	Session 5 (Applications II)
	Afternoon tea
15:00~16:00	Session 2 (FPGA Routing)	15:00~18:00	Social Event (optional)
16:30~17:15	Session 3 (Machine Learning)	18:00~19:00	PhD Forum at Banquet Venue
18:00~20:30	Welcome Reception	19:00~21:00	Banquet

9th December

RFSoC Workshop

10th December

Session 1: Applications 1

Session Chair: Oliver Diessel

• “A Parallel-trial Double-update Annealing Processor for Enabling Highly-effective Solution Search of Constrained Combinatorial Optimization Problems”, A. Hyodo, S. Jimbo, D. Okonogi, T. Van Chu, M. Motomura, K. Kawamura.
• “Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph Analytics”, O. Jaiyeoba, A. Mughrabi, M. Baradaran, B. Gul, K. Skadron.
• “FLUD: A Scalable and Configurable Systolic Array Design for LU Decomposition on FPGAs”, X. Tian, G. Yang, Z. Fang.

Journal Session I

Session Chair: David Boland

• A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis, Yuhan She*, Jierui Liu, Yanlong Huang, Ray Cheung, and Hong Yan
• SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators”, Giovanni Brignone*, Roberto Bosio, Fabrizio Ottati, and Luciano Lavagno
• “CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC”, Tianyou Bao, Pengzhou He, Daisuke Fujimoto, Yuichi Hayashi, and Jiafeng Xie* (jiafeng.xie@villanova.edu)

Session 2: FPGA Routing

Session Chair: Steve Wilton

• MultiQueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism. A. Singer, H. Yan, G. Zhang, M. Jeffrey, M. Stojilović, V. Betz
• FPGA Routing Optimization Based on Multi-Level MUX Architecture. X. Li, K. Shi, W. Luk, H. Zhou, L. Wang
• Parallel FPGA Routing with On-the-Fly Net Decomposition. F. Kosar, M. Stojilović, V. Betz

Session 3: Machine Learning

Session Chair: Jiafeng Xie

• FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers. C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, H. Giefers
• Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs, Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, and Jurgen Teich
• Efficient DSP Packing Method for Neural Network Accelerator. Z. Cui, J. Zhang, W. Tang, H. Chen, J. Liu, M. Zhang, L. Zhang [SHORT]

11th December

Session 4: Programmable Fabrics

Session Chair: Vaughn Betz

• Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs, A. Iyer, N. Pawar, D. Gaitonde, N. Rao
• GraphNoC: Graph Neural Network based Framework and Dataset for Accelerating FPGA based NoCs’ Benchmarking. G. Malik, N. Kapre
• A Regression-based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA Tiles. M. Al-Qawasmi, A. Ye
• Embedded FPGAs for Multi-Project Die Sharing, Dirk Koch, Myrtle Shah, Gavaskar Kanagara, Riadh Ben Abdelhamid, Nguyen Dao

Poster Session I

• Efficient Table-lookup Inference of Binarized Convolutions with Kernel-level Binding on FPGA, Y. Han, H. Li, Q. Liu.
• Design Multi-Model Accelerators via Automatically Extracting Computational Graph Similarities, J. Zhu, B. Han, Q. Lang, D. Zhang, R. Wang, L. Shen.
• Accelerating RaVÆn for Real-time Satellite Image Change Detection, Hongda Zho, Weilin Tao, Oliver Diessel, Cormac Purcell.
• Load Balanced Sparse Bundle Adjustment Accelerator for CNN-Based Visual-Inertial Odometry on FPGA, Y. Xiang, J. Yu, Y. Xu, Y. Hu, K. Guo, Y. Dong, Y. Wang.
• Hardware-Efficient Homogenized Key-Point Selection for Visual SLAM, M. Thathsara, D. Anhettigama, S. Lam, D. Piyasena.
• Field-Programmable Dynamic Deep Learning, Y. Liu, S. Ullah, A. Kumar

Session 5: Applications II

Session Chair: Shinya Takamaeda-Yamazaki

• HEPPO: Hardware-Efficient Proximal Policy Optimization – A Universal Pipelined Architecture for Generalized Advantage Estimation
• TableCache: An Open-Source, Configurable, Last-Level Cache for FPGA Systems. C. Keilbart, L. Shannon
• Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs. Z. Han, Y. Qian, M. Zink, M. Leeser

PhD Forum

• Gradient-Aware Depth Sensitivity Scoring for Optimizing Neural Network Pruning, Z. Yue, D. Yan, S. Ma, C. Sham
• An MLIR-based Compiler for Hardware Acceleration with Recursion Support, J. Li, Z. Zhang, X. Zhou, L. Wang
• CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing, J. Qin, Y. Dai, L. Wang
• Increasing the scalability of graph convolution for FPGA-implemented event-based vision, P. Wzorek, K. Jeziorek, T. Kryjak, A. Pinna

12th December

Session 6: High level Synthesis

Session Chair: Mirjana Stojilovic

• Compass: A Collaborative HLS Design Space Exploration Framework via Graph Representation Learning and Ensemble Bayesian Optimization. H. Kuang, L. Wang
• Resource Dependency-Aware Scheduling for High-Level Synthesis with GNN and SDC. A. Qin, M. Shen, N. Xiao
• TMM-DSE: Topology-Aware MLP-Mixer for QoR Prediction in HLS Design Space Exploration. J. Zhang, J. Pu, H. Chen, X. Li, M. Zhang. [SHORT].

Poster Session II

• A Hardware-Friendly Rotation Convolution Neural Network and its FPGA Implementation for Remote Sensing Scene Classification, X. Li, J. Zhang, J. Xiang, Y. Wang, P. Wang, Y. Wang, F. Xu, M. Zhang, A. Jing
• HBMalloc: Dynamic Memory Management in High-Level Synthesis for FPGA HBM, Y. Mao, Y. Jin, W. Luk, L. Wang.
• FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs, E. Kabir, M. Kabir, A. Downey, J. Bakos, D. Andrews, M. Huang.
• A Table Look-Up based Quantum Simulation Accelerator on an FPGA, H. Hasegawa, M. Shimoda, T. Miyoshi, H. Nakahara.
• IsoFPGA- A Novel CMOS Galvanic Isolation Technique for Remote Physical Attacks in Multi-tenant Cloud FPGA, M. Kawser Ahmed, C. Bobda.
• Optimizing DNN Accelerator Compression Using Tolerable Accuracy Loss, Zhiqiang Que, Anyan Zhao, Jose G. F. Coutinho, Ce Guo, Wayne Luk

Journal Session II

Session Chair: Ameer Abdelhadi

• An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination
• Compressing Neural Networks Using Learnable 1-D Non-Linear Functions
• FPGA Implementation of a Time Series Network Training using Block Minifloat